High-Speed PCBs and Signal Integrity Discussion on DDR5 Memory with Stephen Slater
In the ever-evolving world of technology, the transition from DDR4 to DDR5 memory presents a significant challenge for PCB designers. DDR5, a turning point in the industry, requires a redesign approach that focuses on maintaining clean, matched, and impedance-controlled signal paths with robust grounding and minimal interference sources.
Stephen Slater, a product manager in the High-Speed Digital Simulation Technology at Keysight, emphasizes the importance of advanced design tools such as Pathwave ADS, a flagship product offering schematic simulation, via design, and memory design capabilities. Memory Designer, a product within Pathwave ADS, is particularly useful for pre-layout and full system design for memory.
Best Practices for DDR5 PCB Layout
- Controlled Impedance Routing
- Use controlled impedance traces to match the differential impedance requirements for DDR5 signals, typically 34-40 ohms single-ended or 68-80 ohms differential.
- Maintain consistent trace widths and separations according to stackup and PCB material properties to ensure impedance control.
- Adequate Spacing and Trace Placement
- Keep sufficient spacing between high-speed DDR5 traces to reduce capacitive and inductive coupling that causes crosstalk.
- Route sensitive signals away from noisy or switching signals to minimize interference.
- Ground and Power Plane Integrity
- Provide continuous reference ground planes under high-speed traces to maintain return current paths and reduce loop area that contributes to electromagnetic interference (EMI) and ground bounce noise.
- Use solid power and ground planes with decoupling capacitors placed close to DDR5 power pins to stabilize power delivery and reduce simultaneous switching noise (SSN).
- Minimize Via Use and Discontinuities
- Limit vias on DDR5 signal traces as vias introduce impedance discontinuities and reflections that degrade signal quality.
- Avoid sharp trace bends; use 45-degree bends or curved traces to reduce impedance variance.
- Differential Pair Routing
- Route DDR5 signals as matched differential pairs maintaining tight coupling and equal lengths to reduce differential mode noise and enhance signal integrity.
- Match trace lengths to minimize timing skew.
- Termination and Signal Conditioning
- Implement appropriate termination schemes to damp reflections and improve eye diagram opening.
- Incorporate controlled impedance and termination carefully aligned with DDR5 IC datasheets.
- Component Placement and Board Stackup
- Place DDR5 memory chips and related components close together to minimize trace length and reduce transmission line effects.
- Use a high-quality multilayer PCB stackup with dedicated signal, ground, and power layers optimized for high-speed signaling.
- Simulation and Validation
- Use signal integrity simulation tools to analyze crosstalk, signal reflections, and timing before fabrication.
- Validate with time domain reflectometry (TDR) and vector network analyzer (VNA) measurements on prototypes.
Resources for DDR5 Design
The High-Speed PCB Design Guide, a comprehensive resource consisting of 8 chapters and 115 pages, offers explanations of signal integrity issues, understanding transmission lines and controlled impedance, high-speed PCB material selection, and high-speed layout guidelines. Meanwhile, the Signal Integrity eBook, a 60-minute read, covers topics such as impedance discontinuities, crosstalk, reflections, ringing, via stubs, and more.
As DDR5 designs become more prevalent, Keysight has introduced new tools and resources to support designers. For instance, they have created a library of PCI express-gen-5 reference channels for system simulations and a new conducted EMI analysis tool for power integrity. Additionally, Keysight's scopes offer low-noise capabilities, enabling the recovery of signals even when they are closed.
Crosstalk is a critical issue in the BGA pin field for DDR5, and adjusting the antipad clearance size, number, and location of ground stitching vias can improve signal integrity at 16 Gbps and beyond. Equalization is now on the receiver in DDR5, which can recover a closed signal.
In conclusion, by following these best practices and leveraging the right resources and tools, designers can successfully navigate the challenges of DDR5 PCB layout, ensuring timing accuracy, reducing error rates, and supporting the demanding bandwidth requirements of DDR5 memory.
- The advanced design tools for DDR5 PCB layout, like Pathwave ADS's Memory Designer, are crucial for pre-layout and full system design, particularly in controllable impedance routing, ensuring that controlled impedance traces are used to match the differential impedance requirements for DDR5 signals.
- Data-and-cloud-computing technology relies on the reliable transfer of data, and in handling the move from DDR4 to DDR5 memory, technology such as the minimization of impedance variance through the use of 45-degree bends or curved traces and the implementation of appropriate impedance-controlled termination is pivotal for ensuring signal integrity in the technology-driven world.
